`timescale 1ns / 1ps

`include "soc_define.sv"

module soc_top (
    input  logic                                    osc_clk_25m_i,
    input  logic                                    osc_clk_12288k_i,
    input  logic                                    ext_rst_n_i,
    input  logic                                    uart0_uart_rx_i,
    output logic                                    uart0_uart_tx_o,
    input  logic [               `GPIO_PIN_NUM-1:0] gpio0_gpio_in_i,
    output logic [               `GPIO_PIN_NUM-1:0] gpio0_gpio_out_o,
    output logic [               `GPIO_PIN_NUM-1:0] gpio0_gpio_dir_o,
    output logic [               `GPIO_PIN_NUM-1:0] gpio0_gpio_iof_o,
    output logic [                             3:0] pwm0_pwm_o,
    output logic [                             3:0] pwm1_pwm_o,
    output logic [                             3:0] pwm2_pwm_o,
    input  logic                                    tmr0_capch_i,
    input  logic                                    tmr1_capch_i,
    input  logic                                    tmr2_capch_i,
    input  logic                                    tmr3_capch_i,
    input  logic                                    i2c0_scl_i,
    output logic                                    i2c0_scl_o,
    output logic                                    i2c0_scl_dir_o,
    input  logic                                    i2c0_sda_i,
    output logic                                    i2c0_sda_o,
    output logic                                    i2c0_sda_dir_o,
    output logic                                    spi0_spi_sck_o,
    output logic [                `SPI_NSS_NUM-1:0] spi0_spi_nss_o,
    output logic [                             3:0] spi0_spi_io_en_o,
    input  logic [                             3:0] spi0_spi_io_in_i,
    output logic [                             3:0] spi0_spi_io_out_o,
    output logic                                    spi1_spi_sck_o,
    output logic [                `SPI_NSS_NUM-1:0] spi1_spi_nss_o,
    output logic [                             3:0] spi1_spi_io_en_o,
    input  logic [                             3:0] spi1_spi_io_in_i,
    output logic [                             3:0] spi1_spi_io_out_o,
    output logic [                             4:0] vgalcd0_vgalcd_r_o,
    output logic [                             5:0] vgalcd0_vgalcd_g_o,
    output logic [                             4:0] vgalcd0_vgalcd_b_o,
    output logic                                    vgalcd0_vgalcd_hsync_o,
    output logic                                    vgalcd0_vgalcd_vsync_o,
    output logic                                    vgalcd0_vgalcd_de_o,
    output logic                                    vgalcd0_vgalcd_pclk_o,
    input  logic                                    ps20_ps2_clk_i,
    input  logic                                    ps20_ps2_dat_i,
    input  logic                                    rcu0_pll_en_i,
    input  logic [          `RCU_CLK_CFG_WIDTH-1:0] rcu0_clk_cfg_i,
    input  logic [         `RCU_CORE_SEL_WIDTH-1:0] rcu0_core_sel_i,
    output logic                                    old_ip_spi_flash_clk_o,
    output logic [                             1:0] old_ip_spi_flash_cs_o,
    output logic                                    old_ip_spi_flash_mosi_o,
    input  logic                                    old_ip_spi_flash_miso_i,
    input  logic                                    old_ip_uart_rx_i,
    output logic                                    old_ip_uart_tx_o,
    input  logic                                    old_ip_chiplink_rx_clk_i,
    input  logic                                    old_ip_chiplink_rx_rst_i,
    input  logic                                    old_ip_chiplink_rx_send_i,
    input  logic [`SOCDF_CPLINK_DATA_WIDTH - 1 : 0] old_ip_chiplink_rx_data_i,
    output logic                                    old_ip_chiplink_tx_clk_o,
    output logic                                    old_ip_chiplink_tx_rst_o,
    output logic                                    old_ip_chiplink_tx_send_o,
    output logic [`SOCDF_CPLINK_DATA_WIDTH - 1 : 0] old_ip_chiplink_tx_data_o,
    output logic                                    old_ip_sdram_clk_o,
    output logic                                    old_ip_sdram_cke_o,
    output logic                                    old_ip_sdram_cs_o,
    output logic                                    old_ip_sdram_ras_o,
    output logic                                    old_ip_sdram_cas_o,
    output logic                                    old_ip_sdram_we_o,
    output logic [                             1:0] old_ip_sdram_dqm_o,
    output logic [                            12:0] old_ip_sdram_addr_o,
    output logic [                             1:0] old_ip_sdram_ba_o,
    input  logic [                            15:0] old_ip_sdram_data_input_i,
    output logic [                            15:0] old_ip_sdram_data_output_o,
    output logic                                    old_ip_sdram_data_out_en_o
);

  // wire
  logic [ 3:0] awid_cpu_mst_axi4;
  logic [31:0] awaddr_cpu_mst_axi4;
  logic [ 7:0] awlen_cpu_mst_axi4;
  logic [ 2:0] awsize_cpu_mst_axi4;
  logic [ 1:0] awburst_cpu_mst_axi4;
  logic        awlock_cpu_mst_axi4;
  logic [ 3:0] awcache_cpu_mst_axi4;
  logic [ 2:0] awprot_cpu_mst_axi4;
  logic        awvalid_cpu_mst_axi4;
  logic        awready_cpu_mst_axi4;
  logic [31:0] wdata_cpu_mst_axi4;
  logic [ 3:0] wstrb_cpu_mst_axi4;
  logic        wlast_cpu_mst_axi4;
  logic        wvalid_cpu_mst_axi4;
  logic        wready_cpu_mst_axi4;
  logic [ 2:0] bid_cpu_mst_axi4;
  logic [ 1:0] bresp_cpu_mst_axi4;
  logic        bvalid_cpu_mst_axi4;
  logic        bready_cpu_mst_axi4;
  logic [ 3:0] arid_cpu_mst_axi4;
  logic [31:0] araddr_cpu_mst_axi4;
  logic [ 7:0] arlen_cpu_mst_axi4;
  logic [ 2:0] arsize_cpu_mst_axi4;
  logic [ 1:0] arburst_cpu_mst_axi4;
  logic        arlock_cpu_mst_axi4;
  logic [ 3:0] arcache_cpu_mst_axi4;
  logic [ 2:0] arprot_cpu_mst_axi4;
  logic        arvalid_cpu_mst_axi4;
  logic        arready_cpu_mst_axi4;
  logic [ 2:0] rid_cpu_mst_axi4;
  logic [31:0] rdata_cpu_mst_axi4;
  logic [ 1:0] rresp_cpu_mst_axi4;
  logic        rlast_cpu_mst_axi4;
  logic        rvalid_cpu_mst_axi4;
  logic        rready_cpu_mst_axi4;

  logic [ 3:0] awid_dma_axi4_cpu_m;
  logic [31:0] awaddr_dma_axi4_cpu_m;
  logic [ 7:0] awlen_dma_axi4_cpu_m;
  logic [ 2:0] awsize_dma_axi4_cpu_m;
  logic [ 1:0] awburst_dma_axi4_cpu_m;
  logic        awlock_dma_axi4_cpu_m;
  logic [ 3:0] awcache_dma_axi4_cpu_m;
  logic [ 2:0] awprot_dma_axi4_cpu_m;
  logic        awvalid_dma_axi4_cpu_m;
  logic        awready_dma_axi4_cpu_m;
  logic [31:0] wdata_dma_axi4_cpu_m;
  logic [ 3:0] wstrb_dma_axi4_cpu_m;
  logic        wlast_dma_axi4_cpu_m;
  logic        wvalid_dma_axi4_cpu_m;
  logic        wready_dma_axi4_cpu_m;
  logic [ 3:0] bid_dma_axi4_cpu_m;
  logic [ 1:0] bresp_dma_axi4_cpu_m;
  logic        bvalid_dma_axi4_cpu_m;
  logic        bready_dma_axi4_cpu_m;
  logic [ 3:0] arid_dma_axi4_cpu_m;
  logic [31:0] araddr_dma_axi4_cpu_m;
  logic [ 7:0] arlen_dma_axi4_cpu_m;
  logic [ 2:0] arsize_dma_axi4_cpu_m;
  logic [ 1:0] arburst_dma_axi4_cpu_m;
  logic        arlock_dma_axi4_cpu_m;
  logic [ 3:0] arcache_dma_axi4_cpu_m;
  logic [ 2:0] arprot_dma_axi4_cpu_m;
  logic        arvalid_dma_axi4_cpu_m;
  logic        arready_dma_axi4_cpu_m;
  logic [ 3:0] rid_dma_axi4_cpu_m;
  logic [31:0] rdata_dma_axi4_cpu_m;
  logic [ 1:0] rresp_dma_axi4_cpu_m;
  logic        rlast_dma_axi4_cpu_m;
  logic        rvalid_dma_axi4_cpu_m;
  logic        rready_dma_axi4_cpu_m;

  logic [ 3:0] awid_sdram_slv_axi4;
  logic [31:0] awaddr_sdram_slv_axi4;
  logic [ 7:0] awlen_sdram_slv_axi4;
  logic [ 2:0] awsize_sdram_slv_axi4;
  logic [ 1:0] awburst_sdram_slv_axi4;
  logic        awlock_sdram_slv_axi4;
  logic [ 3:0] awcache_sdram_slv_axi4;
  logic [ 2:0] awprot_sdram_slv_axi4;
  logic        awvalid_sdram_slv_axi4;
  logic        awready_sdram_slv_axi4;
  logic [31:0] wdata_sdram_slv_axi4;
  logic [ 3:0] wstrb_sdram_slv_axi4;
  logic        wlast_sdram_slv_axi4;
  logic        wvalid_sdram_slv_axi4;
  logic        wready_sdram_slv_axi4;
  logic [ 3:0] bid_sdram_slv_axi4;
  logic [ 1:0] bresp_sdram_slv_axi4;
  logic        bvalid_sdram_slv_axi4;
  logic        bready_sdram_slv_axi4;
  logic [ 3:0] arid_sdram_slv_axi4;
  logic [31:0] araddr_sdram_slv_axi4;
  logic [ 7:0] arlen_sdram_slv_axi4;
  logic [ 2:0] arsize_sdram_slv_axi4;
  logic [ 1:0] arburst_sdram_slv_axi4;
  logic        arlock_sdram_slv_axi4;
  logic [ 3:0] arcache_sdram_slv_axi4;
  logic [ 2:0] arprot_sdram_slv_axi4;
  logic        arvalid_sdram_slv_axi4;
  logic        arready_sdram_slv_axi4;
  logic [ 3:0] rid_sdram_slv_axi4;
  logic [31:0] rdata_sdram_slv_axi4;
  logic [ 1:0] rresp_sdram_slv_axi4;
  logic        rlast_sdram_slv_axi4;
  logic        rvalid_sdram_slv_axi4;
  logic        rready_sdram_slv_axi4;

  logic [ 3:0] awid_chiplink_slv_axi4_tpv;
  logic [31:0] awaddr_chiplink_slv_axi4_tpv;
  logic [ 7:0] awlen_chiplink_slv_axi4_tpv;
  logic [ 2:0] awsize_chiplink_slv_axi4_tpv;
  logic [ 1:0] awburst_chiplink_slv_axi4_tpv;
  logic        awlock_chiplink_slv_axi4_tpv;
  logic [ 3:0] awcache_chiplink_slv_axi4_tpv;
  logic [ 2:0] awprot_chiplink_slv_axi4_tpv;
  logic        awvalid_chiplink_slv_axi4_tpv;
  logic        awready_chiplink_slv_axi4_tpv;
  logic [63:0] wdata_chiplink_slv_axi4_tpv;
  logic [ 7:0] wstrb_chiplink_slv_axi4_tpv;
  logic        wlast_chiplink_slv_axi4_tpv;
  logic        wvalid_chiplink_slv_axi4_tpv;
  logic        wready_chiplink_slv_axi4_tpv;
  logic [ 3:0] bid_chiplink_slv_axi4_tpv;
  logic [ 1:0] bresp_chiplink_slv_axi4_tpv;
  logic        bvalid_chiplink_slv_axi4_tpv;
  logic        bready_chiplink_slv_axi4_tpv;
  logic [ 3:0] arid_chiplink_slv_axi4_tpv;
  logic [31:0] araddr_chiplink_slv_axi4_tpv;
  logic [ 7:0] arlen_chiplink_slv_axi4_tpv;
  logic [ 2:0] arsize_chiplink_slv_axi4_tpv;
  logic [ 1:0] arburst_chiplink_slv_axi4_tpv;
  logic        arlock_chiplink_slv_axi4_tpv;
  logic [ 3:0] arcache_chiplink_slv_axi4_tpv;
  logic [ 2:0] arprot_chiplink_slv_axi4_tpv;
  logic        arvalid_chiplink_slv_axi4_tpv;
  logic        arready_chiplink_slv_axi4_tpv;
  logic [ 3:0] rid_chiplink_slv_axi4_tpv;
  logic [63:0] rdata_chiplink_slv_axi4_tpv;
  logic [ 1:0] rresp_chiplink_slv_axi4_tpv;
  logic        rlast_chiplink_slv_axi4_tpv;
  logic        rvalid_chiplink_slv_axi4_tpv;
  logic        rready_chiplink_slv_axi4_tpv;

  logic [ 3:0] awid_dma_axi4_cpu_s;
  logic [31:0] awaddr_dma_axi4_cpu_s;
  logic [ 7:0] awlen_dma_axi4_cpu_s;
  logic [ 2:0] awsize_dma_axi4_cpu_s;
  logic [ 1:0] awburst_dma_axi4_cpu_s;
  logic        awlock_dma_axi4_cpu_s;
  logic [ 3:0] awcache_dma_axi4_cpu_s;
  logic [ 2:0] awprot_dma_axi4_cpu_s;
  logic        awvalid_dma_axi4_cpu_s;
  logic        awready_dma_axi4_cpu_s;
  logic [63:0] wdata_dma_axi4_cpu_s;
  logic [ 7:0] wstrb_dma_axi4_cpu_s;
  logic        wlast_dma_axi4_cpu_s;
  logic        wvalid_dma_axi4_cpu_s;
  logic        wready_dma_axi4_cpu_s;
  logic [ 3:0] bid_dma_axi4_cpu_s;
  logic [ 1:0] bresp_dma_axi4_cpu_s;
  logic        bvalid_dma_axi4_cpu_s;
  logic        bready_dma_axi4_cpu_s;
  logic [ 3:0] arid_dma_axi4_cpu_s;
  logic [31:0] araddr_dma_axi4_cpu_s;
  logic [ 7:0] arlen_dma_axi4_cpu_s;
  logic [ 2:0] arsize_dma_axi4_cpu_s;
  logic [ 1:0] arburst_dma_axi4_cpu_s;
  logic        arlock_dma_axi4_cpu_s;
  logic [ 3:0] arcache_dma_axi4_cpu_s;
  logic [ 2:0] arprot_dma_axi4_cpu_s;
  logic        arvalid_dma_axi4_cpu_s;
  logic        arready_dma_axi4_cpu_s;
  logic [ 3:0] rid_dma_axi4_cpu_s;
  logic [63:0] rdata_dma_axi4_cpu_s;
  logic [ 1:0] rresp_dma_axi4_cpu_s;
  logic        rlast_dma_axi4_cpu_s;
  logic        rvalid_dma_axi4_cpu_s;
  logic        rready_dma_axi4_cpu_s;

  logic [31:0] paddr_spfs_slv_apb4_tpv;
  logic        pselx_spfs_slv_apb4_tpv;
  logic        penable_spfs_slv_apb4_tpv;
  logic        pwrite_spfs_slv_apb4_tpv;
  logic [31:0] prdata_spfs_slv_apb4_tpv;
  logic [31:0] pwdata_spfs_slv_apb4_tpv;
  logic [ 2:0] pprot_spfs_slv_apb4_tpv;
  logic [ 3:0] pstrb_spfs_slv_apb4_tpv;
  logic        pready_spfs_slv_apb4_tpv;
  logic        pslverr_spfs_slv_apb4_tpv;

  logic [31:0] paddr_uart_slv_apb4_tpv;
  logic        pselx_uart_slv_apb4_tpv;
  logic        penable_uart_slv_apb4_tpv;
  logic        pwrite_uart_slv_apb4_tpv;
  logic [31:0] prdata_uart_slv_apb4_tpv;
  logic [31:0] pwdata_uart_slv_apb4_tpv;
  logic [ 2:0] pprot_uart_slv_apb4_tpv;
  logic [ 3:0] pstrb_uart_slv_apb4_tpv;
  logic        pready_uart_slv_apb4_tpv;
  logic        pslverr_uart_slv_apb4_tpv;

  // except
  logic [ 2:0] rid_vgalcd_mst_axi4;
  logic [ 2:0] bid_vgalcd_mst_axi4;

  // clk & rst
  logic clk_core_100_800m, rst_core_100_800m_n;
  logic clk_peri_25m, rst_peri_25m_n;
  logic clk_peri_100m, rst_peri_100m_n;
  logic clk_aud_12288k, rst_aud_12288k_n;
  logic clk_rtc_1k, rst_rtc_1k_n;
  logic clk_test;

  // verilog_format: off
  // new_ip bus interface
  apb4_if u_clint0_apb4_if    (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_plic0_apb4_if     (clk_peri_100m,     rst_peri_100m_n);
  axi4_if u_sram0_axi4_if     (clk_core_100_800m, rst_core_100_800m_n);
  apb4_if u_uart0_apb4_if     (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_gpio0_apb4_if     (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_pwm0_apb4_if      (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_pwm1_apb4_if      (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_pwm2_apb4_if      (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_rtc0_apb4_if      (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_wdg0_apb4_if      (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_tmr0_apb4_if      (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_tmr1_apb4_if      (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_tmr2_apb4_if      (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_tmr3_apb4_if      (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_i2c0_apb4_if      (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_i2s0_apb4_if      (clk_aud_12288k,    rst_aud_12288k_n);
  apb4_if u_spi0_apb4_if      (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_spi1_apb4_if      (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_qspi0_apb4_if     (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_vgalcd0_apb4_if   (clk_peri_100m,     rst_peri_100m_n);
  axi4_if u_vgalcd0_axi4_if   (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_ps20_apb4_if      (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_rng0_apb4_if      (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_crc0_apb4_if      (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_psram0_apb4_if    (clk_peri_100m,     rst_peri_100m_n);
  axi4_if u_psram0_axi4_if    (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_archinfo0_apb4_if (clk_peri_100m,     rst_peri_100m_n);
  apb4_if u_rcu0_apb4_if      (clk_peri_100m,     rst_peri_100m_n);
  // new ip interface
  clint_if  u_clint0_if (clk_rtc_1k);
  plic_if   u_plic0_if ();
  uart_if   u_uart0_if ();
  gpio_if   u_gpio0_if ();
  pwm_if    u_pwm0_if ();
  pwm_if    u_pwm1_if ();
  pwm_if    u_pwm2_if ();
  rtc_if    u_rtc0_if (clk_rtc_1k, rst_rtc_1k_n);
  wdg_if    u_wdg0_if (clk_rtc_1k);
  tmr_if    u_tmr0_if (clk_rtc_1k);
  tmr_if    u_tmr1_if (clk_rtc_1k);
  tmr_if    u_tmr2_if (clk_rtc_1k);
  tmr_if    u_tmr3_if (clk_rtc_1k);
  i2c_if    u_i2c0_if ();
  spi_if    u_spi0_if ();
  spi_if    u_spi1_if ();
  vgalcd_if u_vgalcd0_if ();
  ps2_if    u_ps20_if ();
  rcu_if    u_rcu0_if ();
  // verilog_format: on
  // bind io
  assign u_uart0_if.uart_rx_i       = uart0_uart_rx_i;
  assign uart0_uart_tx_o            = u_uart0_if.uart_tx_o;
  assign u_gpio0_if.gpio_in_i       = gpio0_gpio_in_i;
  assign gpio0_gpio_out_o           = u_gpio0_if.gpio_out_o;
  assign gpio0_gpio_dir_o           = u_gpio0_if.gpio_dir_o;
  assign gpio0_gpio_iof_o           = u_gpio0_if.gpio_iof_o;
  assign pwm0_pwm_o                 = u_pwm0_if.pwm_o;
  assign pwm1_pwm_o                 = u_pwm1_if.pwm_o;
  assign pwm2_pwm_o                 = u_pwm2_if.pwm_o;
  assign u_tmr0_if.capch_i          = tmr0_capch_i;
  assign u_tmr1_if.capch_i          = tmr1_capch_i;
  assign u_tmr2_if.capch_i          = tmr2_capch_i;
  assign u_tmr3_if.capch_i          = tmr3_capch_i;
  assign u_i2c0_if.scl_i            = i2c0_scl_i;
  assign i2c0_scl_o                 = u_i2c0_if.scl_o;
  assign i2c0_scl_dir_o             = u_i2c0_if.scl_dir_o;
  assign u_i2c0_if.sda_i            = i2c0_sda_i;
  assign i2c0_sda_o                 = u_i2c0_if.sda_o;
  assign i2c0_sda_dir_o             = u_i2c0_if.sda_dir_o;
  assign spi0_spi_sck_o             = u_spi0_if.spi_sck_o;
  assign spi0_spi_nss_o             = u_spi0_if.spi_nss_o;
  assign spi0_spi_io_en_o           = u_spi0_if.spi_io_en_o;
  assign u_spi0_if.spi_io_in_i      = spi0_spi_io_in_i;
  assign spi0_spi_io_out_o          = u_spi0_if.spi_io_out_o;
  assign spi1_spi_sck_o             = u_spi1_if.spi_sck_o;
  assign spi1_spi_nss_o             = u_spi1_if.spi_nss_o;
  assign spi1_spi_io_en_o           = u_spi1_if.spi_io_en_o;
  assign u_spi1_if.spi_io_in_i      = spi1_spi_io_in_i;
  assign spi1_spi_io_out_o          = u_spi1_if.spi_io_out_o;
  assign vgalcd0_vgalcd_r_o         = u_vgalcd0_if.vgalcd_r_o;
  assign vgalcd0_vgalcd_g_o         = u_vgalcd0_if.vgalcd_g_o;
  assign vgalcd0_vgalcd_b_o         = u_vgalcd0_if.vgalcd_b_o;
  assign vgalcd0_vgalcd_hsync_o     = u_vgalcd0_if.vgalcd_hsync_o;
  assign vgalcd0_vgalcd_vsync_o     = u_vgalcd0_if.vgalcd_vsync_o;
  assign vgalcd0_vgalcd_de_o        = u_vgalcd0_if.vgalcd_de_o;
  assign vgalcd0_vgalcd_pclk_o      = u_vgalcd0_if.vgalcd_pclk_o;
  assign u_vgalcd0_axi4_if.rid      = {1'b0, rid_vgalcd_mst_axi4};
  assign u_vgalcd0_axi4_if.bid      = {1'b0, bid_vgalcd_mst_axi4};
  assign u_ps20_if.ps2_clk_i        = ps20_ps2_clk_i;
  assign u_ps20_if.ps2_dat_i        = ps20_ps2_dat_i;
  assign u_rcu0_if.ext_lfosc_clk_i  = osc_clk_25m_i;
  assign u_rcu0_if.ext_hfosc_clk_i  = '0;
  assign u_rcu0_if.ext_audosc_clk_i = osc_clk_12288k_i;
  assign u_rcu0_if.ext_rst_n_i      = ext_rst_n_i;
  assign u_rcu0_if.wdt_rst_n_i      = '0;  // just for test
  assign u_rcu0_if.pll_en_i         = rcu0_pll_en_i;
  assign u_rcu0_if.clk_cfg_i        = rcu0_clk_cfg_i;
  assign u_rcu0_if.core_sel_i       = rcu0_core_sel_i;
  // bind clk
  assign clk_core_100_800m          = u_rcu0_if.clk_o[`RCU_CORE_CLK];
  assign rst_core_100_800m_n        = u_rcu0_if.rst_n_o[`RCU_CORE_CLK];
  assign clk_peri_25m               = u_rcu0_if.clk_o[`RCU_LF_PERI_CLK];
  assign rst_peri_25m_n             = u_rcu0_if.rst_n_o[`RCU_LF_PERI_CLK];
  assign clk_peri_100m              = u_rcu0_if.clk_o[`RCU_HF_PERI_CLK];
  assign rst_peri_100m_n            = u_rcu0_if.rst_n_o[`RCU_HF_PERI_CLK];
  assign clk_aud_12288k             = u_rcu0_if.clk_o[`RCU_AUD_CLK];
  assign rst_aud_12288k_n           = u_rcu0_if.rst_n_o[`RCU_AUD_CLK];
  assign clk_rtc_1k                 = u_rcu0_if.clk_o[`RCU_RTC_CLK];
  assign rst_rtc_1k_n               = u_rcu0_if.rst_n_o[`RCU_RTC_CLK];
  assign clk_test                   = u_rcu0_if.clk_o[`RCU_TEST_CLK];

  // new ip inst
  // verilog_format: off
  apb4_clint    u_apb4_clint0    (u_clint0_apb4_if, u_clint0_if);
  apb4_plic     u_apb4_plic0     (u_plic0_apb4_if, u_plic0_if);
  axi4_sram_fsm u_axi4_sram_fsm0 (u_sram0_axi4_if);
  apb4_uart     u_apb4_uart0     (u_uart0_apb4_if, u_uart0_if);
  apb4_gpio     u_apb4_gpio0     (u_gpio0_apb4_if, u_gpio0_if);
  apb4_pwm      u_apb4_pwm0      (u_pwm0_apb4_if, u_pwm0_if);
  apb4_pwm      u_apb4_pwm1      (u_pwm1_apb4_if, u_pwm1_if);
  apb4_pwm      u_apb4_pwm2      (u_pwm2_apb4_if, u_pwm2_if);
  apb4_rtc      u_apb4_rtc0      (u_rtc0_apb4_if, u_rtc0_if);
  apb4_wdg      u_apb4_wdg0      (u_wdg0_apb4_if, u_wdg0_if);
  apb4_tmr      u_apb4_tmr0      (u_tmr0_apb4_if, u_tmr0_if);
  apb4_tmr      u_apb4_tmr1      (u_tmr1_apb4_if, u_tmr1_if);
  apb4_tmr      u_apb4_tmr2      (u_tmr2_apb4_if, u_tmr2_if);
  apb4_tmr      u_apb4_tmr3      (u_tmr3_apb4_if, u_tmr3_if);
  apb4_i2c      u_apb4_i2c0      (u_i2c0_apb4_if, u_i2c0_if);
  apb4_spi      u_apb4_spi0      (u_spi0_apb4_if, u_spi0_if);
  apb4_spi      u_apb4_spi1      (u_spi1_apb4_if, u_spi1_if);
  axi4_vgalcd   u_axi4_vgalcd0   (u_vgalcd0_apb4_if, u_vgalcd0_axi4_if, u_vgalcd0_if);
  apb4_ps2      u_apb4_ps20      (u_ps20_apb4_if, u_ps20_if);
  apb4_rng      u_apb4_rng0      (u_rng0_apb4_if);
  apb4_archinfo u_apb4_archinfo0 (u_archinfo0_apb4_if);
  apb4_rcu      u_apb4_rcu0      (u_rcu0_apb4_if, u_rcu0_if);
 // verilog_format: on

  // =================old ip======================
  ChiplinkBridge u0_ChiplinkBridge (
      .clock                   (clk_peri_25m),
      .reset                   (~rst_peri_25m_n),
      .fpga_io_c2b_clk         (old_ip_chiplink_tx_clk_o),
      .fpga_io_c2b_rst         (old_ip_chiplink_tx_rst_o),
      .fpga_io_c2b_send        (old_ip_chiplink_tx_send_o),
      .fpga_io_c2b_data        (old_ip_chiplink_tx_data_o),
      .fpga_io_b2c_clk         (old_ip_chiplink_rx_clk_i),
      .fpga_io_b2c_rst         (old_ip_chiplink_rx_rst_i),
      .fpga_io_b2c_send        (old_ip_chiplink_rx_send_i),
      .fpga_io_b2c_data        (old_ip_chiplink_rx_data_i),
      //mem axi connect
      .slave_axi4_mem_0_awready(awready_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_awvalid(awvalid_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_awid   (awid_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_awaddr (awaddr_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_awlen  (awlen_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_awsize (awsize_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_awburst(awburst_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_wready (wready_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_wvalid (wvalid_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_wdata  (wdata_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_wstrb  (wstrb_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_wlast  (wlast_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_bready (bready_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_bvalid (bvalid_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_bid    (bid_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_bresp  (bresp_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_arready(arready_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_arvalid(arvalid_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_arid   (arid_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_araddr (araddr_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_arlen  (arlen_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_arsize (arsize_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_arburst(arburst_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_rready (rready_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_rvalid (rvalid_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_rid    (rid_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_rdata  (rdata_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_rresp  (rresp_chiplink_slv_axi4_tpv),
      .slave_axi4_mem_0_rlast  (rlast_chiplink_slv_axi4_tpv),
      //dma axi connect
      .mem_axi4_0_awready      (awready_dma_axi4_cpu_s),
      .mem_axi4_0_awvalid      (awvalid_dma_axi4_cpu_s),
      .mem_axi4_0_awid         (awid_dma_axi4_cpu_s),
      .mem_axi4_0_awaddr       (awaddr_dma_axi4_cpu_s),
      .mem_axi4_0_awlen        (awlen_dma_axi4_cpu_s),
      .mem_axi4_0_awsize       (awsize_dma_axi4_cpu_s),
      .mem_axi4_0_awburst      (awburst_dma_axi4_cpu_s),
      .mem_axi4_0_wready       (wready_dma_axi4_cpu_s),
      .mem_axi4_0_wvalid       (wvalid_dma_axi4_cpu_s),
      .mem_axi4_0_wdata        (wdata_dma_axi4_cpu_s),
      .mem_axi4_0_wstrb        (wstrb_dma_axi4_cpu_s),
      .mem_axi4_0_wlast        (wlast_dma_axi4_cpu_s),
      .mem_axi4_0_bready       (bready_dma_axi4_cpu_s),
      .mem_axi4_0_bvalid       (bvalid_dma_axi4_cpu_s),
      .mem_axi4_0_bid          (bid_dma_axi4_cpu_s),
      .mem_axi4_0_bresp        (bresp_dma_axi4_cpu_s),
      .mem_axi4_0_arready      (arready_dma_axi4_cpu_s),
      .mem_axi4_0_arvalid      (arvalid_dma_axi4_cpu_s),
      .mem_axi4_0_arid         (arid_dma_axi4_cpu_s),
      .mem_axi4_0_araddr       (araddr_dma_axi4_cpu_s),
      .mem_axi4_0_arlen        (arlen_dma_axi4_cpu_s),
      .mem_axi4_0_arsize       (arsize_dma_axi4_cpu_s),
      .mem_axi4_0_arburst      (arburst_dma_axi4_cpu_s),
      .mem_axi4_0_rready       (rready_dma_axi4_cpu_s),
      .mem_axi4_0_rvalid       (rvalid_dma_axi4_cpu_s),
      .mem_axi4_0_rid          (rid_dma_axi4_cpu_s),
      .mem_axi4_0_rdata        (rdata_dma_axi4_cpu_s),
      .mem_axi4_0_rresp        (rresp_dma_axi4_cpu_s),
      .mem_axi4_0_rlast        (rlast_dma_axi4_cpu_s)
  );

  spi_flash #(
      .flash_addr_start(`SOCDF_SPI_FLASH_START),
      .flash_addr_end  (`SOCDF_SPI_FLASH_END),
      .spi_cs_num      (2)
  ) u0_spi_flash (
      .pclk       (clk_peri_25m),
      .presetn    (rst_peri_25m_n),
      .paddr      ({paddr_spfs_slv_apb4_tpv[`SOCDF_P_ADDR_W-1:2], 2'd0}),
      .psel       (pselx_spfs_slv_apb4_tpv),
      .penable    (penable_spfs_slv_apb4_tpv),
      .pwrite     (pwrite_spfs_slv_apb4_tpv),
      .pwdata     (pwdata_spfs_slv_apb4_tpv),
      .pwstrb     (pstrb_spfs_slv_apb4_tpv),
      .prdata     (prdata_spfs_slv_apb4_tpv),
      .pslverr    (pslverr_spfs_slv_apb4_tpv),
      .pready     (pready_spfs_slv_apb4_tpv),
      .spi_clk    (old_ip_spi_flash_clk_o),
      .spi_cs     (old_ip_spi_flash_cs_o),
      .spi_mosi   (old_ip_spi_flash_mosi_o),
      .spi_miso   (old_ip_spi_flash_miso_i),
      .spi_irq_out()
  );

  uart_apb u0_uart_apb (
      .clk       (clk_peri_25m),
      .resetn    (rst_peri_25m_n),
      .in_psel   (pselx_uart_slv_apb4_tpv),
      .in_penable(penable_uart_slv_apb4_tpv),
      .in_pprot  (pprot_uart_slv_apb4_tpv),
      .in_pready (pready_uart_slv_apb4_tpv),
      .in_pslverr(pslverr_uart_slv_apb4_tpv),
      .in_paddr  (paddr_uart_slv_apb4_tpv),
      .in_pwrite (pwrite_uart_slv_apb4_tpv),
      .in_prdata (prdata_uart_slv_apb4_tpv),
      .in_pwdata (pwdata_uart_slv_apb4_tpv),
      .in_pstrb  (pstrb_uart_slv_apb4_tpv),
      .uart_rx   (old_ip_uart_rx_i),
      .uart_tx   (old_ip_uart_tx_o)
  );

  sdram_axi #(
        .SDRAM_MHZ         (100)
      , .SDRAM_ADDR_W      (25)
      , .SDRAM_COL_W       (10)
      , .SDRAM_READ_LATENCY(2)
  ) u0_sdram_axi (
      // Inputs
      .clk_i              (clk_peri_100m),
      .rst_i              (~rst_peri_100m_n),
      .inport_awvalid_i   (awvalid_sdram_slv_axi4),
      .inport_awaddr_i    (awaddr_sdram_slv_axi4),
      .inport_awid_i      (awid_sdram_slv_axi4),
      .inport_awlen_i     (awlen_sdram_slv_axi4),
      .inport_awburst_i   (awburst_sdram_slv_axi4),
      .inport_wvalid_i    (wvalid_sdram_slv_axi4),
      .inport_wdata_i     (wdata_sdram_slv_axi4),
      .inport_wstrb_i     (wstrb_sdram_slv_axi4),
      .inport_wlast_i     (wlast_sdram_slv_axi4),
      .inport_bready_i    (bready_sdram_slv_axi4),
      .inport_arvalid_i   (arvalid_sdram_slv_axi4),
      .inport_araddr_i    (araddr_sdram_slv_axi4),
      .inport_arid_i      (arid_sdram_slv_axi4),
      .inport_arlen_i     (arlen_sdram_slv_axi4),
      .inport_arburst_i   (arburst_sdram_slv_axi4),
      .inport_rready_i    (rready_sdram_slv_axi4),
      .sdram_data_input_i (old_ip_sdram_data_input_i),
      // Outputs
      .inport_awready_o   (awready_sdram_slv_axi4),
      .inport_wready_o    (wready_sdram_slv_axi4),
      .inport_bvalid_o    (bvalid_sdram_slv_axi4),
      .inport_bresp_o     (bresp_sdram_slv_axi4),
      .inport_bid_o       (bid_sdram_slv_axi4),
      .inport_arready_o   (arready_sdram_slv_axi4),
      .inport_rvalid_o    (rvalid_sdram_slv_axi4),
      .inport_rdata_o     (rdata_sdram_slv_axi4),
      .inport_rresp_o     (rresp_sdram_slv_axi4),
      .inport_rid_o       (rid_sdram_slv_axi4),
      .inport_rlast_o     (rlast_sdram_slv_axi4),
      .sdram_clk_o        (old_ip_sdram_clk_o),
      .sdram_cke_o        (old_ip_sdram_cke_o),
      .sdram_cs_o         (old_ip_sdram_cs_o),
      .sdram_ras_o        (old_ip_sdram_ras_o),
      .sdram_cas_o        (old_ip_sdram_cas_o),
      .sdram_we_o         (old_ip_sdram_we_o),
      .sdram_dqm_o        (old_ip_sdram_dqm_o),
      .sdram_addr_o       (old_ip_sdram_addr_o),
      .sdram_ba_o         (old_ip_sdram_ba_o),
      .sdram_data_output_o(old_ip_sdram_data_output_o),
      .sdram_data_out_en_o(old_ip_sdram_data_out_en_o)
  );

  // core
  Top u0_top (
      .clock            (clk_core_100_800m),
      .reset            (~rst_core_100_800m_n),
      .io_interrupt     (1'b0),
      .io_master_awready(awready_cpu_mst_axi4),
      .io_master_awvalid(awvalid_cpu_mst_axi4),
      .io_master_awaddr (awaddr_cpu_mst_axi4),
      .io_master_awid   (awid_cpu_mst_axi4),
      .io_master_awlen  (awlen_cpu_mst_axi4),
      .io_master_awsize (awsize_cpu_mst_axi4),
      .io_master_awburst(awburst_cpu_mst_axi4),
      .io_master_wready (wready_cpu_mst_axi4),
      .io_master_wvalid (wvalid_cpu_mst_axi4),
      .io_master_wdata  (wdata_cpu_mst_axi4),
      .io_master_wstrb  (wstrb_cpu_mst_axi4),
      .io_master_wlast  (wlast_cpu_mst_axi4),
      .io_master_bready (bready_cpu_mst_axi4),
      .io_master_bvalid (bvalid_cpu_mst_axi4),
      .io_master_bresp  (bresp_cpu_mst_axi4),
      .io_master_bid    ({1'b0, bid_cpu_mst_axi4}),
      .io_master_arready(arready_cpu_mst_axi4),
      .io_master_arvalid(arvalid_cpu_mst_axi4),
      .io_master_araddr (araddr_cpu_mst_axi4),
      .io_master_arid   (arid_cpu_mst_axi4),
      .io_master_arlen  (arlen_cpu_mst_axi4),
      .io_master_arsize (arsize_cpu_mst_axi4),
      .io_master_arburst(arburst_cpu_mst_axi4),
      .io_master_rready (rready_cpu_mst_axi4),
      .io_master_rvalid (rvalid_cpu_mst_axi4),
      .io_master_rresp  (rresp_cpu_mst_axi4),
      .io_master_rdata  (rdata_cpu_mst_axi4),
      .io_master_rlast  (rlast_cpu_mst_axi4),
      .io_master_rid    ({1'b0, rid_cpu_mst_axi4}),

      .io_slave_awready(awready_dma_axi4_cpu_m),
      .io_slave_awvalid(awvalid_dma_axi4_cpu_m),
      .io_slave_awaddr (awaddr_dma_axi4_cpu_m),
      .io_slave_awid   (awid_dma_axi4_cpu_m),
      .io_slave_awlen  (awlen_dma_axi4_cpu_m),
      .io_slave_awsize (awsize_dma_axi4_cpu_m),
      .io_slave_awburst(awburst_dma_axi4_cpu_m),
      .io_slave_wready (wready_dma_axi4_cpu_m),
      .io_slave_wvalid (wvalid_dma_axi4_cpu_m),
      .io_slave_wdata  (wdata_dma_axi4_cpu_m),
      .io_slave_wstrb  (wstrb_dma_axi4_cpu_m),
      .io_slave_wlast  (wlast_dma_axi4_cpu_m),
      .io_slave_bready (bready_dma_axi4_cpu_m),
      .io_slave_bvalid (bvalid_dma_axi4_cpu_m),
      .io_slave_bresp  (bresp_dma_axi4_cpu_m),
      .io_slave_bid    (bid_dma_axi4_cpu_m),
      .io_slave_arready(arready_dma_axi4_cpu_m),
      .io_slave_arvalid(arvalid_dma_axi4_cpu_m),
      .io_slave_araddr (araddr_dma_axi4_cpu_m),
      .io_slave_arid   (arid_dma_axi4_cpu_m),
      .io_slave_arlen  (arlen_dma_axi4_cpu_m),
      .io_slave_arsize (arsize_dma_axi4_cpu_m),
      .io_slave_arburst(arburst_dma_axi4_cpu_m),
      .io_slave_rready (rready_dma_axi4_cpu_m),
      .io_slave_rvalid (rvalid_dma_axi4_cpu_m),
      .io_slave_rresp  (rresp_dma_axi4_cpu_m),
      .io_slave_rdata  (rdata_dma_axi4_cpu_m),
      .io_slave_rlast  (rlast_dma_axi4_cpu_m),
      .io_slave_rid    (rid_dma_axi4_cpu_m)
  );

  // bus
  nic400_ysyx_rv32 u0_nic400_ysyx_rv32 (
      // Instance: u_cd_clk_aud_12288k, Port: i2s_slv_apb4
      .paddr_i2s_slv_apb4           (u_i2s0_apb4_if.paddr),
      .pselx_i2s_slv_apb4           (u_i2s0_apb4_if.psel),
      .penable_i2s_slv_apb4         (u_i2s0_apb4_if.penable),
      .pwrite_i2s_slv_apb4          (u_i2s0_apb4_if.pwrite),
      .prdata_i2s_slv_apb4          (u_i2s0_apb4_if.prdata),
      .pwdata_i2s_slv_apb4          (u_i2s0_apb4_if.pwdata),
      .pprot_i2s_slv_apb4           (u_i2s0_apb4_if.pprot),
      .pstrb_i2s_slv_apb4           (u_i2s0_apb4_if.pstrb),
      .pready_i2s_slv_apb4          (u_i2s0_apb4_if.pready),
      .pslverr_i2s_slv_apb4         (u_i2s0_apb4_if.pslverr),
      // Instance: u_cd_clk_core_100_800m, Port: cpu_mst_axi4
      .awid_cpu_mst_axi4            (awid_cpu_mst_axi4[2:0]),
      .awaddr_cpu_mst_axi4          (awaddr_cpu_mst_axi4),
      .awlen_cpu_mst_axi4           (awlen_cpu_mst_axi4),
      .awsize_cpu_mst_axi4          (awsize_cpu_mst_axi4),
      .awburst_cpu_mst_axi4         (awburst_cpu_mst_axi4),
      .awlock_cpu_mst_axi4          (awlock_cpu_mst_axi4),
      .awcache_cpu_mst_axi4         (awcache_cpu_mst_axi4),
      .awprot_cpu_mst_axi4          (awprot_cpu_mst_axi4),
      .awvalid_cpu_mst_axi4         (awvalid_cpu_mst_axi4),
      .awready_cpu_mst_axi4         (awready_cpu_mst_axi4),
      .wdata_cpu_mst_axi4           (wdata_cpu_mst_axi4),
      .wstrb_cpu_mst_axi4           (wstrb_cpu_mst_axi4),
      .wlast_cpu_mst_axi4           (wlast_cpu_mst_axi4),
      .wvalid_cpu_mst_axi4          (wvalid_cpu_mst_axi4),
      .wready_cpu_mst_axi4          (wready_cpu_mst_axi4),
      .bid_cpu_mst_axi4             (bid_cpu_mst_axi4),
      .bresp_cpu_mst_axi4           (bresp_cpu_mst_axi4),
      .bvalid_cpu_mst_axi4          (bvalid_cpu_mst_axi4),
      .bready_cpu_mst_axi4          (bready_cpu_mst_axi4),
      .arid_cpu_mst_axi4            (arid_cpu_mst_axi4[2:0]),
      .araddr_cpu_mst_axi4          (araddr_cpu_mst_axi4),
      .arlen_cpu_mst_axi4           (arlen_cpu_mst_axi4),
      .arsize_cpu_mst_axi4          (arsize_cpu_mst_axi4),
      .arburst_cpu_mst_axi4         (arburst_cpu_mst_axi4),
      .arlock_cpu_mst_axi4          (arlock_cpu_mst_axi4),
      .arcache_cpu_mst_axi4         (arcache_cpu_mst_axi4),
      .arprot_cpu_mst_axi4          (arprot_cpu_mst_axi4),
      .arvalid_cpu_mst_axi4         (arvalid_cpu_mst_axi4),
      .arready_cpu_mst_axi4         (arready_cpu_mst_axi4),
      .rid_cpu_mst_axi4             (rid_cpu_mst_axi4),
      .rdata_cpu_mst_axi4           (rdata_cpu_mst_axi4),
      .rresp_cpu_mst_axi4           (rresp_cpu_mst_axi4),
      .rlast_cpu_mst_axi4           (rlast_cpu_mst_axi4),
      .rvalid_cpu_mst_axi4          (rvalid_cpu_mst_axi4),
      .rready_cpu_mst_axi4          (rready_cpu_mst_axi4),
      // Instance: u_cd_clk_core_100_800m, Port: dma_axi4_cpu_m
      .awid_dma_axi4_cpu_m          (awid_dma_axi4_cpu_m),
      .awaddr_dma_axi4_cpu_m        (awaddr_dma_axi4_cpu_m),
      .awlen_dma_axi4_cpu_m         (awlen_dma_axi4_cpu_m),
      .awsize_dma_axi4_cpu_m        (awsize_dma_axi4_cpu_m),
      .awburst_dma_axi4_cpu_m       (awburst_dma_axi4_cpu_m),
      .awlock_dma_axi4_cpu_m        (awlock_dma_axi4_cpu_m),
      .awcache_dma_axi4_cpu_m       (awcache_dma_axi4_cpu_m),
      .awprot_dma_axi4_cpu_m        (awprot_dma_axi4_cpu_m),
      .awvalid_dma_axi4_cpu_m       (awvalid_dma_axi4_cpu_m),
      .awready_dma_axi4_cpu_m       (awready_dma_axi4_cpu_m),
      .wdata_dma_axi4_cpu_m         (wdata_dma_axi4_cpu_m),
      .wstrb_dma_axi4_cpu_m         (wstrb_dma_axi4_cpu_m),
      .wlast_dma_axi4_cpu_m         (wlast_dma_axi4_cpu_m),
      .wvalid_dma_axi4_cpu_m        (wvalid_dma_axi4_cpu_m),
      .wready_dma_axi4_cpu_m        (wready_dma_axi4_cpu_m),
      .bid_dma_axi4_cpu_m           (bid_dma_axi4_cpu_m),
      .bresp_dma_axi4_cpu_m         (bresp_dma_axi4_cpu_m),
      .bvalid_dma_axi4_cpu_m        (bvalid_dma_axi4_cpu_m),
      .bready_dma_axi4_cpu_m        (bready_dma_axi4_cpu_m),
      .arid_dma_axi4_cpu_m          (arid_dma_axi4_cpu_m),
      .araddr_dma_axi4_cpu_m        (araddr_dma_axi4_cpu_m),
      .arlen_dma_axi4_cpu_m         (arlen_dma_axi4_cpu_m),
      .arsize_dma_axi4_cpu_m        (arsize_dma_axi4_cpu_m),
      .arburst_dma_axi4_cpu_m       (arburst_dma_axi4_cpu_m),
      .arlock_dma_axi4_cpu_m        (arlock_dma_axi4_cpu_m),
      .arcache_dma_axi4_cpu_m       (arcache_dma_axi4_cpu_m),
      .arprot_dma_axi4_cpu_m        (arprot_dma_axi4_cpu_m),
      .arvalid_dma_axi4_cpu_m       (arvalid_dma_axi4_cpu_m),
      .arready_dma_axi4_cpu_m       (arready_dma_axi4_cpu_m),
      .rid_dma_axi4_cpu_m           (rid_dma_axi4_cpu_m),
      .rdata_dma_axi4_cpu_m         (rdata_dma_axi4_cpu_m),
      .rresp_dma_axi4_cpu_m         (rresp_dma_axi4_cpu_m),
      .rlast_dma_axi4_cpu_m         (rlast_dma_axi4_cpu_m),
      .rvalid_dma_axi4_cpu_m        (rvalid_dma_axi4_cpu_m),
      .rready_dma_axi4_cpu_m        (rready_dma_axi4_cpu_m),
      // Instance: u_cd_clk_core_100_800m, Port: sram_slv_axi4
      .awid_sram_slv_axi4           (u_sram0_axi4_if.awid),
      .awaddr_sram_slv_axi4         (u_sram0_axi4_if.awaddr),
      .awlen_sram_slv_axi4          (u_sram0_axi4_if.awlen),
      .awsize_sram_slv_axi4         (u_sram0_axi4_if.awsize),
      .awburst_sram_slv_axi4        (u_sram0_axi4_if.awburst),
      .awlock_sram_slv_axi4         (u_sram0_axi4_if.awlock),
      .awcache_sram_slv_axi4        (u_sram0_axi4_if.awcache),
      .awprot_sram_slv_axi4         (u_sram0_axi4_if.awprot),
      .awvalid_sram_slv_axi4        (u_sram0_axi4_if.awvalid),
      .awready_sram_slv_axi4        (u_sram0_axi4_if.awready),
      .wdata_sram_slv_axi4          (u_sram0_axi4_if.wdata),
      .wstrb_sram_slv_axi4          (u_sram0_axi4_if.wstrb),
      .wlast_sram_slv_axi4          (u_sram0_axi4_if.wlast),
      .wvalid_sram_slv_axi4         (u_sram0_axi4_if.wvalid),
      .wready_sram_slv_axi4         (u_sram0_axi4_if.wready),
      .bid_sram_slv_axi4            (u_sram0_axi4_if.bid),
      .bresp_sram_slv_axi4          (u_sram0_axi4_if.bresp),
      .bvalid_sram_slv_axi4         (u_sram0_axi4_if.bvalid),
      .bready_sram_slv_axi4         (u_sram0_axi4_if.bready),
      .arid_sram_slv_axi4           (u_sram0_axi4_if.arid),
      .araddr_sram_slv_axi4         (u_sram0_axi4_if.araddr),
      .arlen_sram_slv_axi4          (u_sram0_axi4_if.arlen),
      .arsize_sram_slv_axi4         (u_sram0_axi4_if.arsize),
      .arburst_sram_slv_axi4        (u_sram0_axi4_if.arburst),
      .arlock_sram_slv_axi4         (u_sram0_axi4_if.arlock),
      .arcache_sram_slv_axi4        (u_sram0_axi4_if.arcache),
      .arprot_sram_slv_axi4         (u_sram0_axi4_if.arprot),
      .arvalid_sram_slv_axi4        (u_sram0_axi4_if.arvalid),
      .arready_sram_slv_axi4        (u_sram0_axi4_if.arready),
      .rid_sram_slv_axi4            (u_sram0_axi4_if.rid),
      .rdata_sram_slv_axi4          (u_sram0_axi4_if.rdata),
      .rresp_sram_slv_axi4          (u_sram0_axi4_if.rresp),
      .rlast_sram_slv_axi4          (u_sram0_axi4_if.rlast),
      .rvalid_sram_slv_axi4         (u_sram0_axi4_if.rvalid),
      .rready_sram_slv_axi4         (u_sram0_axi4_if.rready),
      // Instance: u_cd_clk_peri_100m, Port: archinfo_slv_apb4
      .paddr_archinfo_slv_apb4      (u_archinfo0_apb4_if.paddr),
      .pselx_archinfo_slv_apb4      (u_archinfo0_apb4_if.psel),
      .penable_archinfo_slv_apb4    (u_archinfo0_apb4_if.penable),
      .pwrite_archinfo_slv_apb4     (u_archinfo0_apb4_if.pwrite),
      .prdata_archinfo_slv_apb4     (u_archinfo0_apb4_if.prdata),
      .pwdata_archinfo_slv_apb4     (u_archinfo0_apb4_if.pwdata),
      .pprot_archinfo_slv_apb4      (u_archinfo0_apb4_if.pprot),
      .pstrb_archinfo_slv_apb4      (u_archinfo0_apb4_if.pstrb),
      .pready_archinfo_slv_apb4     (u_archinfo0_apb4_if.pready),
      .pslverr_archinfo_slv_apb4    (u_archinfo0_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: clint_slv_apb4
      .paddr_clint_slv_apb4         (u_clint0_apb4_if.paddr),
      .pselx_clint_slv_apb4         (u_clint0_apb4_if.psel),
      .penable_clint_slv_apb4       (u_clint0_apb4_if.penable),
      .pwrite_clint_slv_apb4        (u_clint0_apb4_if.pwrite),
      .prdata_clint_slv_apb4        (u_clint0_apb4_if.prdata),
      .pwdata_clint_slv_apb4        (u_clint0_apb4_if.pwdata),
      .pprot_clint_slv_apb4         (u_clint0_apb4_if.pprot),
      .pstrb_clint_slv_apb4         (u_clint0_apb4_if.pstrb),
      .pready_clint_slv_apb4        (u_clint0_apb4_if.pready),
      .pslverr_clint_slv_apb4       (u_clint0_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: crc_slv_apb4
      .paddr_crc_slv_apb4           (u_crc0_apb4_if.paddr),
      .pselx_crc_slv_apb4           (u_crc0_apb4_if.psel),
      .penable_crc_slv_apb4         (u_crc0_apb4_if.penable),
      .pwrite_crc_slv_apb4          (u_crc0_apb4_if.pwrite),
      .prdata_crc_slv_apb4          (u_crc0_apb4_if.prdata),
      .pwdata_crc_slv_apb4          (u_crc0_apb4_if.pwdata),
      .pprot_crc_slv_apb4           (u_crc0_apb4_if.pprot),
      .pstrb_crc_slv_apb4           (u_crc0_apb4_if.pstrb),
      .pready_crc_slv_apb4          (u_crc0_apb4_if.pready),
      .pslverr_crc_slv_apb4         (u_crc0_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: gpio_slv_apb4
      .paddr_gpio_slv_apb4          (u_gpio0_apb4_if.paddr),
      .pselx_gpio_slv_apb4          (u_gpio0_apb4_if.psel),
      .penable_gpio_slv_apb4        (u_gpio0_apb4_if.penable),
      .pwrite_gpio_slv_apb4         (u_gpio0_apb4_if.pwrite),
      .prdata_gpio_slv_apb4         (u_gpio0_apb4_if.prdata),
      .pwdata_gpio_slv_apb4         (u_gpio0_apb4_if.pwdata),
      .pprot_gpio_slv_apb4          (u_gpio0_apb4_if.pprot),
      .pstrb_gpio_slv_apb4          (u_gpio0_apb4_if.pstrb),
      .pready_gpio_slv_apb4         (u_gpio0_apb4_if.pready),
      .pslverr_gpio_slv_apb4        (u_gpio0_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: i2c_slv_apb4
      .paddr_i2c_slv_apb4           (u_i2c0_apb4_if.paddr),
      .pselx_i2c_slv_apb4           (u_i2c0_apb4_if.psel),
      .penable_i2c_slv_apb4         (u_i2c0_apb4_if.penable),
      .pwrite_i2c_slv_apb4          (u_i2c0_apb4_if.pwrite),
      .prdata_i2c_slv_apb4          (u_i2c0_apb4_if.prdata),
      .pwdata_i2c_slv_apb4          (u_i2c0_apb4_if.pwdata),
      .pprot_i2c_slv_apb4           (u_i2c0_apb4_if.pprot),
      .pstrb_i2c_slv_apb4           (u_i2c0_apb4_if.pstrb),
      .pready_i2c_slv_apb4          (u_i2c0_apb4_if.pready),
      .pslverr_i2c_slv_apb4         (u_i2c0_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: plic_slv_apb4
      .paddr_plic_slv_apb4          (u_plic0_apb4_if.paddr),
      .pselx_plic_slv_apb4          (u_plic0_apb4_if.psel),
      .penable_plic_slv_apb4        (u_plic0_apb4_if.penable),
      .pwrite_plic_slv_apb4         (u_plic0_apb4_if.pwrite),
      .prdata_plic_slv_apb4         (u_plic0_apb4_if.prdata),
      .pwdata_plic_slv_apb4         (u_plic0_apb4_if.pwdata),
      .pprot_plic_slv_apb4          (u_plic0_apb4_if.pprot),
      .pstrb_plic_slv_apb4          (u_plic0_apb4_if.pstrb),
      .pready_plic_slv_apb4         (u_plic0_apb4_if.pready),
      .pslverr_plic_slv_apb4        (u_plic0_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: ps2_slv_apb4
      .paddr_ps2_slv_apb4           (u_ps20_apb4_if.paddr),
      .pselx_ps2_slv_apb4           (u_ps20_apb4_if.psel),
      .penable_ps2_slv_apb4         (u_ps20_apb4_if.penable),
      .pwrite_ps2_slv_apb4          (u_ps20_apb4_if.pwrite),
      .prdata_ps2_slv_apb4          (u_ps20_apb4_if.prdata),
      .pwdata_ps2_slv_apb4          (u_ps20_apb4_if.pwdata),
      .pprot_ps2_slv_apb4           (u_ps20_apb4_if.pprot),
      .pstrb_ps2_slv_apb4           (u_ps20_apb4_if.pstrb),
      .pready_ps2_slv_apb4          (u_ps20_apb4_if.pready),
      .pslverr_ps2_slv_apb4         (u_ps20_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: psram_slv_apb4
      .paddr_psram_slv_apb4         (u_psram0_apb4_if.paddr),
      .pselx_psram_slv_apb4         (u_psram0_apb4_if.psel),
      .penable_psram_slv_apb4       (u_psram0_apb4_if.penable),
      .pwrite_psram_slv_apb4        (u_psram0_apb4_if.pwrite),
      .prdata_psram_slv_apb4        (u_psram0_apb4_if.prdata),
      .pwdata_psram_slv_apb4        (u_psram0_apb4_if.pwdata),
      .pprot_psram_slv_apb4         (u_psram0_apb4_if.pprot),
      .pstrb_psram_slv_apb4         (u_psram0_apb4_if.pstrb),
      .pready_psram_slv_apb4        (u_psram0_apb4_if.pready),
      .pslverr_psram_slv_apb4       (u_psram0_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: psram_slv_axi4
      .awid_psram_slv_axi4          (u_psram0_axi4_if.awid),
      .awaddr_psram_slv_axi4        (u_psram0_axi4_if.awaddr),
      .awlen_psram_slv_axi4         (u_psram0_axi4_if.awlen),
      .awsize_psram_slv_axi4        (u_psram0_axi4_if.awsize),
      .awburst_psram_slv_axi4       (u_psram0_axi4_if.awburst),
      .awlock_psram_slv_axi4        (u_psram0_axi4_if.awlock),
      .awcache_psram_slv_axi4       (u_psram0_axi4_if.awcache),
      .awprot_psram_slv_axi4        (u_psram0_axi4_if.awprot),
      .awvalid_psram_slv_axi4       (u_psram0_axi4_if.awvalid),
      .awready_psram_slv_axi4       (u_psram0_axi4_if.awready),
      .wdata_psram_slv_axi4         (u_psram0_axi4_if.wdata),
      .wstrb_psram_slv_axi4         (u_psram0_axi4_if.wstrb),
      .wlast_psram_slv_axi4         (u_psram0_axi4_if.wlast),
      .wvalid_psram_slv_axi4        (u_psram0_axi4_if.wvalid),
      .wready_psram_slv_axi4        (u_psram0_axi4_if.wready),
      .bid_psram_slv_axi4           (u_psram0_axi4_if.bid),
      .bresp_psram_slv_axi4         (u_psram0_axi4_if.bresp),
      .bvalid_psram_slv_axi4        (u_psram0_axi4_if.bvalid),
      .bready_psram_slv_axi4        (u_psram0_axi4_if.bready),
      .arid_psram_slv_axi4          (u_psram0_axi4_if.arid),
      .araddr_psram_slv_axi4        (u_psram0_axi4_if.araddr),
      .arlen_psram_slv_axi4         (u_psram0_axi4_if.arlen),
      .arsize_psram_slv_axi4        (u_psram0_axi4_if.arsize),
      .arburst_psram_slv_axi4       (u_psram0_axi4_if.arburst),
      .arlock_psram_slv_axi4        (u_psram0_axi4_if.arlock),
      .arcache_psram_slv_axi4       (u_psram0_axi4_if.arcache),
      .arprot_psram_slv_axi4        (u_psram0_axi4_if.arprot),
      .arvalid_psram_slv_axi4       (u_psram0_axi4_if.arvalid),
      .arready_psram_slv_axi4       (u_psram0_axi4_if.arready),
      .rid_psram_slv_axi4           (u_psram0_axi4_if.rid),
      .rdata_psram_slv_axi4         (u_psram0_axi4_if.rdata),
      .rresp_psram_slv_axi4         (u_psram0_axi4_if.rresp),
      .rlast_psram_slv_axi4         (u_psram0_axi4_if.rlast),
      .rvalid_psram_slv_axi4        (u_psram0_axi4_if.rvalid),
      .rready_psram_slv_axi4        (u_psram0_axi4_if.rready),
      // Instance: u_cd_clk_peri_100m, Port: pwm0_slv_apb4
      .paddr_pwm0_slv_apb4          (u_pwm0_apb4_if.paddr),
      .pselx_pwm0_slv_apb4          (u_pwm0_apb4_if.psel),
      .penable_pwm0_slv_apb4        (u_pwm0_apb4_if.penable),
      .pwrite_pwm0_slv_apb4         (u_pwm0_apb4_if.pwrite),
      .prdata_pwm0_slv_apb4         (u_pwm0_apb4_if.prdata),
      .pwdata_pwm0_slv_apb4         (u_pwm0_apb4_if.pwdata),
      .pprot_pwm0_slv_apb4          (u_pwm0_apb4_if.pprot),
      .pstrb_pwm0_slv_apb4          (u_pwm0_apb4_if.pstrb),
      .pready_pwm0_slv_apb4         (u_pwm0_apb4_if.pready),
      .pslverr_pwm0_slv_apb4        (u_pwm0_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: pwm1_slv_apb4
      .paddr_pwm1_slv_apb4          (u_pwm1_apb4_if.paddr),
      .pselx_pwm1_slv_apb4          (u_pwm1_apb4_if.psel),
      .penable_pwm1_slv_apb4        (u_pwm1_apb4_if.penable),
      .pwrite_pwm1_slv_apb4         (u_pwm1_apb4_if.pwrite),
      .prdata_pwm1_slv_apb4         (u_pwm1_apb4_if.prdata),
      .pwdata_pwm1_slv_apb4         (u_pwm1_apb4_if.pwdata),
      .pprot_pwm1_slv_apb4          (u_pwm1_apb4_if.pprot),
      .pstrb_pwm1_slv_apb4          (u_pwm1_apb4_if.pstrb),
      .pready_pwm1_slv_apb4         (u_pwm1_apb4_if.pready),
      .pslverr_pwm1_slv_apb4        (u_pwm1_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: pwm2_slv_apb4
      .paddr_pwm2_slv_apb4          (u_pwm2_apb4_if.paddr),
      .pselx_pwm2_slv_apb4          (u_pwm2_apb4_if.psel),
      .penable_pwm2_slv_apb4        (u_pwm2_apb4_if.penable),
      .pwrite_pwm2_slv_apb4         (u_pwm2_apb4_if.pwrite),
      .prdata_pwm2_slv_apb4         (u_pwm2_apb4_if.prdata),
      .pwdata_pwm2_slv_apb4         (u_pwm2_apb4_if.pwdata),
      .pprot_pwm2_slv_apb4          (u_pwm2_apb4_if.pprot),
      .pstrb_pwm2_slv_apb4          (u_pwm2_apb4_if.pstrb),
      .pready_pwm2_slv_apb4         (u_pwm2_apb4_if.pready),
      .pslverr_pwm2_slv_apb4        (u_pwm2_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: qspi_slv_apb4
      .paddr_qspi_slv_apb4          (u_qspi0_apb4_if.paddr),
      .pselx_qspi_slv_apb4          (u_qspi0_apb4_if.psel),
      .penable_qspi_slv_apb4        (u_qspi0_apb4_if.penable),
      .pwrite_qspi_slv_apb4         (u_qspi0_apb4_if.pwrite),
      .prdata_qspi_slv_apb4         (u_qspi0_apb4_if.prdata),
      .pwdata_qspi_slv_apb4         (u_qspi0_apb4_if.pwdata),
      .pprot_qspi_slv_apb4          (u_qspi0_apb4_if.pprot),
      .pstrb_qspi_slv_apb4          (u_qspi0_apb4_if.pstrb),
      .pready_qspi_slv_apb4         (u_qspi0_apb4_if.pready),
      .pslverr_qspi_slv_apb4        (u_qspi0_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: rcu_slv_apb4
      .paddr_rcu_slv_apb4           (u_rcu0_apb4_if.paddr),
      .pselx_rcu_slv_apb4           (u_rcu0_apb4_if.psel),
      .penable_rcu_slv_apb4         (u_rcu0_apb4_if.penable),
      .pwrite_rcu_slv_apb4          (u_rcu0_apb4_if.pwrite),
      .prdata_rcu_slv_apb4          (u_rcu0_apb4_if.prdata),
      .pwdata_rcu_slv_apb4          (u_rcu0_apb4_if.pwdata),
      .pprot_rcu_slv_apb4           (u_rcu0_apb4_if.pprot),
      .pstrb_rcu_slv_apb4           (u_rcu0_apb4_if.pstrb),
      .pready_rcu_slv_apb4          (u_rcu0_apb4_if.pready),
      .pslverr_rcu_slv_apb4         (u_rcu0_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: rng_slv_apb4
      .paddr_rng_slv_apb4           (u_rng0_apb4_if.paddr),
      .pselx_rng_slv_apb4           (u_rng0_apb4_if.psel),
      .penable_rng_slv_apb4         (u_rng0_apb4_if.penable),
      .pwrite_rng_slv_apb4          (u_rng0_apb4_if.pwrite),
      .prdata_rng_slv_apb4          (u_rng0_apb4_if.prdata),
      .pwdata_rng_slv_apb4          (u_rng0_apb4_if.pwdata),
      .pprot_rng_slv_apb4           (u_rng0_apb4_if.pprot),
      .pstrb_rng_slv_apb4           (u_rng0_apb4_if.pstrb),
      .pready_rng_slv_apb4          (u_rng0_apb4_if.pready),
      .pslverr_rng_slv_apb4         (u_rng0_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: rtc_slv_apb4
      .paddr_rtc_slv_apb4           (u_rtc0_apb4_if.paddr),
      .pselx_rtc_slv_apb4           (u_rtc0_apb4_if.psel),
      .penable_rtc_slv_apb4         (u_rtc0_apb4_if.penable),
      .pwrite_rtc_slv_apb4          (u_rtc0_apb4_if.pwrite),
      .prdata_rtc_slv_apb4          (u_rtc0_apb4_if.prdata),
      .pwdata_rtc_slv_apb4          (u_rtc0_apb4_if.pwdata),
      .pprot_rtc_slv_apb4           (u_rtc0_apb4_if.pprot),
      .pstrb_rtc_slv_apb4           (u_rtc0_apb4_if.pstrb),
      .pready_rtc_slv_apb4          (u_rtc0_apb4_if.pready),
      .pslverr_rtc_slv_apb4         (u_rtc0_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: sdram_slv_axi4
      .awid_sdram_slv_axi4          (awid_sdram_slv_axi4),
      .awaddr_sdram_slv_axi4        (awaddr_sdram_slv_axi4),
      .awlen_sdram_slv_axi4         (awlen_sdram_slv_axi4),
      .awsize_sdram_slv_axi4        (awsize_sdram_slv_axi4),
      .awburst_sdram_slv_axi4       (awburst_sdram_slv_axi4),
      .awlock_sdram_slv_axi4        (awlock_sdram_slv_axi4),
      .awcache_sdram_slv_axi4       (awcache_sdram_slv_axi4),
      .awprot_sdram_slv_axi4        (awprot_sdram_slv_axi4),
      .awvalid_sdram_slv_axi4       (awvalid_sdram_slv_axi4),
      .awready_sdram_slv_axi4       (awready_sdram_slv_axi4),
      .wdata_sdram_slv_axi4         (wdata_sdram_slv_axi4),
      .wstrb_sdram_slv_axi4         (wstrb_sdram_slv_axi4),
      .wlast_sdram_slv_axi4         (wlast_sdram_slv_axi4),
      .wvalid_sdram_slv_axi4        (wvalid_sdram_slv_axi4),
      .wready_sdram_slv_axi4        (wready_sdram_slv_axi4),
      .bid_sdram_slv_axi4           (bid_sdram_slv_axi4),
      .bresp_sdram_slv_axi4         (bresp_sdram_slv_axi4),
      .bvalid_sdram_slv_axi4        (bvalid_sdram_slv_axi4),
      .bready_sdram_slv_axi4        (bready_sdram_slv_axi4),
      .arid_sdram_slv_axi4          (arid_sdram_slv_axi4),
      .araddr_sdram_slv_axi4        (araddr_sdram_slv_axi4),
      .arlen_sdram_slv_axi4         (arlen_sdram_slv_axi4),
      .arsize_sdram_slv_axi4        (arsize_sdram_slv_axi4),
      .arburst_sdram_slv_axi4       (arburst_sdram_slv_axi4),
      .arlock_sdram_slv_axi4        (arlock_sdram_slv_axi4),
      .arcache_sdram_slv_axi4       (arcache_sdram_slv_axi4),
      .arprot_sdram_slv_axi4        (arprot_sdram_slv_axi4),
      .arvalid_sdram_slv_axi4       (arvalid_sdram_slv_axi4),
      .arready_sdram_slv_axi4       (arready_sdram_slv_axi4),
      .rid_sdram_slv_axi4           (rid_sdram_slv_axi4),
      .rdata_sdram_slv_axi4         (rdata_sdram_slv_axi4),
      .rresp_sdram_slv_axi4         (rresp_sdram_slv_axi4),
      .rlast_sdram_slv_axi4         (rlast_sdram_slv_axi4),
      .rvalid_sdram_slv_axi4        (rvalid_sdram_slv_axi4),
      .rready_sdram_slv_axi4        (rready_sdram_slv_axi4),
      // Instance: u_cd_clk_peri_100m, Port: spi0_slv_apb4
      .paddr_spi0_slv_apb4          (u_spi0_apb4_if.paddr),
      .pselx_spi0_slv_apb4          (u_spi0_apb4_if.psel),
      .penable_spi0_slv_apb4        (u_spi0_apb4_if.penable),
      .pwrite_spi0_slv_apb4         (u_spi0_apb4_if.pwrite),
      .prdata_spi0_slv_apb4         (u_spi0_apb4_if.prdata),
      .pwdata_spi0_slv_apb4         (u_spi0_apb4_if.pwdata),
      .pprot_spi0_slv_apb4          (u_spi0_apb4_if.pprot),
      .pstrb_spi0_slv_apb4          (u_spi0_apb4_if.pstrb),
      .pready_spi0_slv_apb4         (u_spi0_apb4_if.pready),
      .pslverr_spi0_slv_apb4        (u_spi0_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: spi1_slv_apb4
      .paddr_spi1_slv_apb4          (u_spi1_apb4_if.paddr),
      .pselx_spi1_slv_apb4          (u_spi1_apb4_if.psel),
      .penable_spi1_slv_apb4        (u_spi1_apb4_if.penable),
      .pwrite_spi1_slv_apb4         (u_spi1_apb4_if.pwrite),
      .prdata_spi1_slv_apb4         (u_spi1_apb4_if.prdata),
      .pwdata_spi1_slv_apb4         (u_spi1_apb4_if.pwdata),
      .pprot_spi1_slv_apb4          (u_spi1_apb4_if.pprot),
      .pstrb_spi1_slv_apb4          (u_spi1_apb4_if.pstrb),
      .pready_spi1_slv_apb4         (u_spi1_apb4_if.pready),
      .pslverr_spi1_slv_apb4        (u_spi1_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: tim0_slv_apb4
      .paddr_tim0_slv_apb4          (u_tmr0_apb4_if.paddr),
      .pselx_tim0_slv_apb4          (u_tmr0_apb4_if.psel),
      .penable_tim0_slv_apb4        (u_tmr0_apb4_if.penable),
      .pwrite_tim0_slv_apb4         (u_tmr0_apb4_if.pwrite),
      .prdata_tim0_slv_apb4         (u_tmr0_apb4_if.prdata),
      .pwdata_tim0_slv_apb4         (u_tmr0_apb4_if.pwdata),
      .pprot_tim0_slv_apb4          (u_tmr0_apb4_if.pprot),
      .pstrb_tim0_slv_apb4          (u_tmr0_apb4_if.pstrb),
      .pready_tim0_slv_apb4         (u_tmr0_apb4_if.pready),
      .pslverr_tim0_slv_apb4        (u_tmr0_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: tim1_slv_apb4
      .paddr_tim1_slv_apb4          (u_tmr1_apb4_if.paddr),
      .pselx_tim1_slv_apb4          (u_tmr1_apb4_if.psel),
      .penable_tim1_slv_apb4        (u_tmr1_apb4_if.penable),
      .pwrite_tim1_slv_apb4         (u_tmr1_apb4_if.pwrite),
      .prdata_tim1_slv_apb4         (u_tmr1_apb4_if.prdata),
      .pwdata_tim1_slv_apb4         (u_tmr1_apb4_if.pwdata),
      .pprot_tim1_slv_apb4          (u_tmr1_apb4_if.pprot),
      .pstrb_tim1_slv_apb4          (u_tmr1_apb4_if.pstrb),
      .pready_tim1_slv_apb4         (u_tmr1_apb4_if.pready),
      .pslverr_tim1_slv_apb4        (u_tmr1_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: tim2_slv_apb4
      .paddr_tim2_slv_apb4          (u_tmr2_apb4_if.paddr),
      .pselx_tim2_slv_apb4          (u_tmr2_apb4_if.psel),
      .penable_tim2_slv_apb4        (u_tmr2_apb4_if.penable),
      .pwrite_tim2_slv_apb4         (u_tmr2_apb4_if.pwrite),
      .prdata_tim2_slv_apb4         (u_tmr2_apb4_if.prdata),
      .pwdata_tim2_slv_apb4         (u_tmr2_apb4_if.pwdata),
      .pprot_tim2_slv_apb4          (u_tmr2_apb4_if.pprot),
      .pstrb_tim2_slv_apb4          (u_tmr2_apb4_if.pstrb),
      .pready_tim2_slv_apb4         (u_tmr2_apb4_if.pready),
      .pslverr_tim2_slv_apb4        (u_tmr2_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: tim3_slv_apb4
      .paddr_tim3_slv_apb4          (u_tmr3_apb4_if.paddr),
      .pselx_tim3_slv_apb4          (u_tmr3_apb4_if.psel),
      .penable_tim3_slv_apb4        (u_tmr3_apb4_if.penable),
      .pwrite_tim3_slv_apb4         (u_tmr3_apb4_if.pwrite),
      .prdata_tim3_slv_apb4         (u_tmr3_apb4_if.prdata),
      .pwdata_tim3_slv_apb4         (u_tmr3_apb4_if.pwdata),
      .pprot_tim3_slv_apb4          (u_tmr3_apb4_if.pprot),
      .pstrb_tim3_slv_apb4          (u_tmr3_apb4_if.pstrb),
      .pready_tim3_slv_apb4         (u_tmr3_apb4_if.pready),
      .pslverr_tim3_slv_apb4        (u_tmr3_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: uart_slv_apb4
      .paddr_uart_slv_apb4          (u_uart0_apb4_if.paddr),
      .pselx_uart_slv_apb4          (u_uart0_apb4_if.psel),
      .penable_uart_slv_apb4        (u_uart0_apb4_if.penable),
      .pwrite_uart_slv_apb4         (u_uart0_apb4_if.pwrite),
      .prdata_uart_slv_apb4         (u_uart0_apb4_if.prdata),
      .pwdata_uart_slv_apb4         (u_uart0_apb4_if.pwdata),
      .pprot_uart_slv_apb4          (u_uart0_apb4_if.pprot),
      .pstrb_uart_slv_apb4          (u_uart0_apb4_if.pstrb),
      .pready_uart_slv_apb4         (u_uart0_apb4_if.pready),
      .pslverr_uart_slv_apb4        (u_uart0_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: vgalcd_mst_axi4
      .awid_vgalcd_mst_axi4         (u_vgalcd0_axi4_if.awid[2:0]),
      .awaddr_vgalcd_mst_axi4       (u_vgalcd0_axi4_if.awaddr),
      .awlen_vgalcd_mst_axi4        (u_vgalcd0_axi4_if.awlen),
      .awsize_vgalcd_mst_axi4       (u_vgalcd0_axi4_if.awsize),
      .awburst_vgalcd_mst_axi4      (u_vgalcd0_axi4_if.awburst),
      .awlock_vgalcd_mst_axi4       (u_vgalcd0_axi4_if.awlock),
      .awcache_vgalcd_mst_axi4      (u_vgalcd0_axi4_if.awcache),
      .awprot_vgalcd_mst_axi4       (u_vgalcd0_axi4_if.awprot),
      .awvalid_vgalcd_mst_axi4      (u_vgalcd0_axi4_if.awvalid),
      .awready_vgalcd_mst_axi4      (u_vgalcd0_axi4_if.awready),
      .wdata_vgalcd_mst_axi4        (u_vgalcd0_axi4_if.wdata),
      .wstrb_vgalcd_mst_axi4        (u_vgalcd0_axi4_if.wstrb),
      .wlast_vgalcd_mst_axi4        (u_vgalcd0_axi4_if.wlast),
      .wvalid_vgalcd_mst_axi4       (u_vgalcd0_axi4_if.wvalid),
      .wready_vgalcd_mst_axi4       (u_vgalcd0_axi4_if.wready),
      .bid_vgalcd_mst_axi4          (bid_vgalcd_mst_axi4),
      .bresp_vgalcd_mst_axi4        (u_vgalcd0_axi4_if.bresp),
      .bvalid_vgalcd_mst_axi4       (u_vgalcd0_axi4_if.bvalid),
      .bready_vgalcd_mst_axi4       (u_vgalcd0_axi4_if.bready),
      .arid_vgalcd_mst_axi4         (u_vgalcd0_axi4_if.arid[2:0]),
      .araddr_vgalcd_mst_axi4       (u_vgalcd0_axi4_if.araddr),
      .arlen_vgalcd_mst_axi4        (u_vgalcd0_axi4_if.arlen),
      .arsize_vgalcd_mst_axi4       (u_vgalcd0_axi4_if.arsize),
      .arburst_vgalcd_mst_axi4      (u_vgalcd0_axi4_if.arburst),
      .arlock_vgalcd_mst_axi4       (u_vgalcd0_axi4_if.arlock),
      .arcache_vgalcd_mst_axi4      (u_vgalcd0_axi4_if.arcache),
      .arprot_vgalcd_mst_axi4       (u_vgalcd0_axi4_if.arprot),
      .arvalid_vgalcd_mst_axi4      (u_vgalcd0_axi4_if.arvalid),
      .arready_vgalcd_mst_axi4      (u_vgalcd0_axi4_if.arready),
      .rid_vgalcd_mst_axi4          (rid_vgalcd_mst_axi4),
      .rdata_vgalcd_mst_axi4        (u_vgalcd0_axi4_if.rdata),
      .rresp_vgalcd_mst_axi4        (u_vgalcd0_axi4_if.rresp),
      .rlast_vgalcd_mst_axi4        (u_vgalcd0_axi4_if.rlast),
      .rvalid_vgalcd_mst_axi4       (u_vgalcd0_axi4_if.rvalid),
      .rready_vgalcd_mst_axi4       (u_vgalcd0_axi4_if.rready),
      // Instance: u_cd_clk_peri_100m, Port: vgalcd_slv_apb4
      .paddr_vgalcd_slv_apb4        (u_vgalcd0_apb4_if.paddr),
      .pselx_vgalcd_slv_apb4        (u_vgalcd0_apb4_if.psel),
      .penable_vgalcd_slv_apb4      (u_vgalcd0_apb4_if.penable),
      .pwrite_vgalcd_slv_apb4       (u_vgalcd0_apb4_if.pwrite),
      .prdata_vgalcd_slv_apb4       (u_vgalcd0_apb4_if.prdata),
      .pwdata_vgalcd_slv_apb4       (u_vgalcd0_apb4_if.pwdata),
      .pprot_vgalcd_slv_apb4        (u_vgalcd0_apb4_if.pprot),
      .pstrb_vgalcd_slv_apb4        (u_vgalcd0_apb4_if.pstrb),
      .pready_vgalcd_slv_apb4       (u_vgalcd0_apb4_if.pready),
      .pslverr_vgalcd_slv_apb4      (u_vgalcd0_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_100m, Port: wdg_slv_apb4
      .paddr_wdg_slv_apb4           (u_wdg0_apb4_if.paddr),
      .pselx_wdg_slv_apb4           (u_wdg0_apb4_if.psel),
      .penable_wdg_slv_apb4         (u_wdg0_apb4_if.penable),
      .pwrite_wdg_slv_apb4          (u_wdg0_apb4_if.pwrite),
      .prdata_wdg_slv_apb4          (u_wdg0_apb4_if.prdata),
      .pwdata_wdg_slv_apb4          (u_wdg0_apb4_if.pwdata),
      .pprot_wdg_slv_apb4           (u_wdg0_apb4_if.pprot),
      .pstrb_wdg_slv_apb4           (u_wdg0_apb4_if.pstrb),
      .pready_wdg_slv_apb4          (u_wdg0_apb4_if.pready),
      .pslverr_wdg_slv_apb4         (u_wdg0_apb4_if.pslverr),
      // Instance: u_cd_clk_peri_25m, Port: chiplink_slv_axi4_tpv
      .awid_chiplink_slv_axi4_tpv   (awid_chiplink_slv_axi4_tpv),
      .awaddr_chiplink_slv_axi4_tpv (awaddr_chiplink_slv_axi4_tpv),
      .awlen_chiplink_slv_axi4_tpv  (awlen_chiplink_slv_axi4_tpv),
      .awsize_chiplink_slv_axi4_tpv (awsize_chiplink_slv_axi4_tpv),
      .awburst_chiplink_slv_axi4_tpv(awburst_chiplink_slv_axi4_tpv),
      .awlock_chiplink_slv_axi4_tpv (awlock_chiplink_slv_axi4_tpv),
      .awcache_chiplink_slv_axi4_tpv(awcache_chiplink_slv_axi4_tpv),
      .awprot_chiplink_slv_axi4_tpv (awprot_chiplink_slv_axi4_tpv),
      .awvalid_chiplink_slv_axi4_tpv(awvalid_chiplink_slv_axi4_tpv),
      .awready_chiplink_slv_axi4_tpv(awready_chiplink_slv_axi4_tpv),
      .wdata_chiplink_slv_axi4_tpv  (wdata_chiplink_slv_axi4_tpv),
      .wstrb_chiplink_slv_axi4_tpv  (wstrb_chiplink_slv_axi4_tpv),
      .wlast_chiplink_slv_axi4_tpv  (wlast_chiplink_slv_axi4_tpv),
      .wvalid_chiplink_slv_axi4_tpv (wvalid_chiplink_slv_axi4_tpv),
      .wready_chiplink_slv_axi4_tpv (wready_chiplink_slv_axi4_tpv),
      .bid_chiplink_slv_axi4_tpv    (bid_chiplink_slv_axi4_tpv),
      .bresp_chiplink_slv_axi4_tpv  (bresp_chiplink_slv_axi4_tpv),
      .bvalid_chiplink_slv_axi4_tpv (bvalid_chiplink_slv_axi4_tpv),
      .bready_chiplink_slv_axi4_tpv (bready_chiplink_slv_axi4_tpv),
      .arid_chiplink_slv_axi4_tpv   (arid_chiplink_slv_axi4_tpv),
      .araddr_chiplink_slv_axi4_tpv (araddr_chiplink_slv_axi4_tpv),
      .arlen_chiplink_slv_axi4_tpv  (arlen_chiplink_slv_axi4_tpv),
      .arsize_chiplink_slv_axi4_tpv (arsize_chiplink_slv_axi4_tpv),
      .arburst_chiplink_slv_axi4_tpv(arburst_chiplink_slv_axi4_tpv),
      .arlock_chiplink_slv_axi4_tpv (arlock_chiplink_slv_axi4_tpv),
      .arcache_chiplink_slv_axi4_tpv(arcache_chiplink_slv_axi4_tpv),
      .arprot_chiplink_slv_axi4_tpv (arprot_chiplink_slv_axi4_tpv),
      .arvalid_chiplink_slv_axi4_tpv(arvalid_chiplink_slv_axi4_tpv),
      .arready_chiplink_slv_axi4_tpv(arready_chiplink_slv_axi4_tpv),
      .rid_chiplink_slv_axi4_tpv    (rid_chiplink_slv_axi4_tpv),
      .rdata_chiplink_slv_axi4_tpv  (rdata_chiplink_slv_axi4_tpv),
      .rresp_chiplink_slv_axi4_tpv  (rresp_chiplink_slv_axi4_tpv),
      .rlast_chiplink_slv_axi4_tpv  (rlast_chiplink_slv_axi4_tpv),
      .rvalid_chiplink_slv_axi4_tpv (rvalid_chiplink_slv_axi4_tpv),
      .rready_chiplink_slv_axi4_tpv (rready_chiplink_slv_axi4_tpv),
      // Instance: u_cd_clk_peri_25m, Port: dma_axi4_cpu_s
      .awid_dma_axi4_cpu_s          (awid_dma_axi4_cpu_s),
      .awaddr_dma_axi4_cpu_s        (awaddr_dma_axi4_cpu_s),
      .awlen_dma_axi4_cpu_s         (awlen_dma_axi4_cpu_s),
      .awsize_dma_axi4_cpu_s        (awsize_dma_axi4_cpu_s),
      .awburst_dma_axi4_cpu_s       (awburst_dma_axi4_cpu_s),
      .awlock_dma_axi4_cpu_s        (awlock_dma_axi4_cpu_s),
      .awcache_dma_axi4_cpu_s       (awcache_dma_axi4_cpu_s),
      .awprot_dma_axi4_cpu_s        (awprot_dma_axi4_cpu_s),
      .awvalid_dma_axi4_cpu_s       (awvalid_dma_axi4_cpu_s),
      .awready_dma_axi4_cpu_s       (awready_dma_axi4_cpu_s),
      .wdata_dma_axi4_cpu_s         (wdata_dma_axi4_cpu_s),
      .wstrb_dma_axi4_cpu_s         (wstrb_dma_axi4_cpu_s),
      .wlast_dma_axi4_cpu_s         (wlast_dma_axi4_cpu_s),
      .wvalid_dma_axi4_cpu_s        (wvalid_dma_axi4_cpu_s),
      .wready_dma_axi4_cpu_s        (wready_dma_axi4_cpu_s),
      .bid_dma_axi4_cpu_s           (bid_dma_axi4_cpu_s),
      .bresp_dma_axi4_cpu_s         (bresp_dma_axi4_cpu_s),
      .bvalid_dma_axi4_cpu_s        (bvalid_dma_axi4_cpu_s),
      .bready_dma_axi4_cpu_s        (bready_dma_axi4_cpu_s),
      .arid_dma_axi4_cpu_s          (arid_dma_axi4_cpu_s),
      .araddr_dma_axi4_cpu_s        (araddr_dma_axi4_cpu_s),
      .arlen_dma_axi4_cpu_s         (arlen_dma_axi4_cpu_s),
      .arsize_dma_axi4_cpu_s        (arsize_dma_axi4_cpu_s),
      .arburst_dma_axi4_cpu_s       (arburst_dma_axi4_cpu_s),
      .arlock_dma_axi4_cpu_s        (arlock_dma_axi4_cpu_s),
      .arcache_dma_axi4_cpu_s       (arcache_dma_axi4_cpu_s),
      .arprot_dma_axi4_cpu_s        (arprot_dma_axi4_cpu_s),
      .arvalid_dma_axi4_cpu_s       (arvalid_dma_axi4_cpu_s),
      .arready_dma_axi4_cpu_s       (arready_dma_axi4_cpu_s),
      .rid_dma_axi4_cpu_s           (rid_dma_axi4_cpu_s),
      .rdata_dma_axi4_cpu_s         (rdata_dma_axi4_cpu_s),
      .rresp_dma_axi4_cpu_s         (rresp_dma_axi4_cpu_s),
      .rlast_dma_axi4_cpu_s         (rlast_dma_axi4_cpu_s),
      .rvalid_dma_axi4_cpu_s        (rvalid_dma_axi4_cpu_s),
      .rready_dma_axi4_cpu_s        (rready_dma_axi4_cpu_s),
      // Instance: u_cd_clk_peri_25m, Port: spfs_slv_apb4_tpv
      .paddr_spfs_slv_apb4_tpv      (paddr_spfs_slv_apb4_tpv),
      .pselx_spfs_slv_apb4_tpv      (pselx_spfs_slv_apb4_tpv),
      .penable_spfs_slv_apb4_tpv    (penable_spfs_slv_apb4_tpv),
      .pwrite_spfs_slv_apb4_tpv     (pwrite_spfs_slv_apb4_tpv),
      .prdata_spfs_slv_apb4_tpv     (prdata_spfs_slv_apb4_tpv),
      .pwdata_spfs_slv_apb4_tpv     (pwdata_spfs_slv_apb4_tpv),
      .pprot_spfs_slv_apb4_tpv      (pprot_spfs_slv_apb4_tpv),
      .pstrb_spfs_slv_apb4_tpv      (pstrb_spfs_slv_apb4_tpv),
      .pready_spfs_slv_apb4_tpv     (pready_spfs_slv_apb4_tpv),
      .pslverr_spfs_slv_apb4_tpv    (pslverr_spfs_slv_apb4_tpv),
      // Instance: u_cd_clk_peri_25m, Port: uart_slv_apb4_tpv
      .paddr_uart_slv_apb4_tpv      (paddr_uart_slv_apb4_tpv),
      .pselx_uart_slv_apb4_tpv      (pselx_uart_slv_apb4_tpv),
      .penable_uart_slv_apb4_tpv    (penable_uart_slv_apb4_tpv),
      .pwrite_uart_slv_apb4_tpv     (pwrite_uart_slv_apb4_tpv),
      .prdata_uart_slv_apb4_tpv     (prdata_uart_slv_apb4_tpv),
      .pwdata_uart_slv_apb4_tpv     (pwdata_uart_slv_apb4_tpv),
      .pprot_uart_slv_apb4_tpv      (pprot_uart_slv_apb4_tpv),
      .pstrb_uart_slv_apb4_tpv      (pstrb_uart_slv_apb4_tpv),
      .pready_uart_slv_apb4_tpv     (pready_uart_slv_apb4_tpv),
      .pslverr_uart_slv_apb4_tpv    (pslverr_uart_slv_apb4_tpv),
      //  Non-bus signals
      .clk_aud_12288kclk            (clk_aud_12288k),
      .clk_aud_12288kclken          (1'b1),
      .clk_aud_12288kresetn         (rst_aud_12288k_n),
      .clk_core_200_800mclk         (clk_core_100_800m),
      .clk_core_200_800mresetn      (rst_core_100_800m_n),
      .clk_peri_100mclk             (clk_peri_100m),
      .clk_peri_100mclken           (1'b1),
      .clk_peri_100mresetn          (rst_peri_100m_n),
      .clk_peri_25mclk              (clk_peri_25m),
      .clk_peri_25mclken            (1'b1),
      .clk_peri_25mresetn           (rst_peri_25m_n)
  );

endmodule
